adviceLUNA / TRQer Support
When using cores which equipped with L2 cache, is there any disadvantage if none is selected for L2C setting of MPU-specific settings?
[Scope of application]
Cortex cores which can be equipped with ARM L2 cache.
[Question]
It debugs cortex core system which can be equipped with ARM L2 cache. I'm not sure what is the base address of L2C, so I select none for L2C type, which is on the Others tab of MPU-specific setting of microVIEW-PLUS. Is there any disadvantage?
[Answer]
Select none for L2C type, which is on the Others tab of MPU-specific setting if you are not sure about the base address of L2 cache (Base address of L2C control register).
If you select none for L2C type, ICE cannot control cache when operating memory by specifying the physical address by adding “p" at the beginning of address when dumping memory or editing memory. Therefore it cannot maintain the coherency. It may access the cache.
If you did not specify the physical address by adding “p" at the beginning of address, there is no disadvantage.
Cortex cores which can be equipped with ARM L2 cache.
[Question]
It debugs cortex core system which can be equipped with ARM L2 cache. I'm not sure what is the base address of L2C, so I select none for L2C type, which is on the Others tab of MPU-specific setting of microVIEW-PLUS. Is there any disadvantage?
[Answer]
Select none for L2C type, which is on the Others tab of MPU-specific setting if you are not sure about the base address of L2 cache (Base address of L2C control register).
If you select none for L2C type, ICE cannot control cache when operating memory by specifying the physical address by adding “p" at the beginning of address when dumping memory or editing memory. Therefore it cannot maintain the coherency. It may access the cache.
If you did not specify the physical address by adding “p" at the beginning of address, there is no disadvantage.
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